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PLL-Phase Locked Loops

Phase Locked Loops are a fundamental building block in Frequency Synthesizer Design and routinely used in many applications. Much literature exists on design and simulation methods. A critical aspect of phase locked loop design for low noise applications is a clear and intuitive understanding of the noise contributions of components in various parts of the loop. This area seems to be less understood and not explicitly stated in much of the literature. Derivation of noise transfer functions and some key points for phase locked loop noise analysis is provided along with a simulation and measured example.

A basic phase locked loop block diagram is shown in Figure 1. The phase detector produces a signal proportional to the phase difference of the two input signals. The integrator adjusts the VCO tuning voltage to minimize the output of the phase detector and thus phase locks the VCO to a reference input signal. References [] provide detailed descriptions of the phase locked loop process.

The phase locked loop circuit of Figure 1 can be constructed in a control system block diagram form as shown in Figure 2. Again, references [] provide thorough derivations of this method.

Every component in the loop adds noise to the circuit. Noise sources can be added to the control model as shown in Figure 3. Noise transfer functions will be derived for each contributor to overall output phase noise. Many forms of loop filters exist and have been demonstrated. For this analysis, a loop filter of the form shown in Figure 4 is assumed. This form is typical of many used in low noise phase locked loop design. Filter Gain is set by R 1 and R F. A typical response of this filter is shown in Figure 5.

The Loop Filter response can be considered in three general regions. The 1st region is an integrator. Loop gain in this region provides the mechanism for the VCO to track the reference oscillator. In order to ensure stability, a zero is typically applied in the loop filter forming the middle region of nearly constant gain. An additional pole after loop bandwidth provides additional filtering of the reference noise and forms the third region of additional filtering.

These regions have either a constant gain or a constant roll-off. The constant gain region can be written as K F. Note that K F is different in each region, but is a constant that can be used in evaluating the PLL transfer function for each region. Considering the loop response based on these regions can provide rapid insight to noise contributions from various parts of the loop.

Each noise source can be considered in terms of a traditional feedback system as shown in Figure 6. A s B s represents the closed loop path. Noise transfer functions will be derived with this method. Starting with the Reference noise, we can write the forward gain A s , and feedback B s as;. In the frequency offset region where the loop filter is a constant gain, K F , the loop filter becomes. This is 1st order low pass function. The bandwidth of this low pass filter is the PLL loop bandwidth and is.

Equation 5 is a 2nd order low pass function with no damping. An important observation with this equation is that a loop filter of on ideal integrator will be unstable. In practice a zero is added before the PLL loop bandwidth to bring the transfer function closer to equation 3. To get additional rejection above the loop bandwidth an additional pole can be added to ensure a 2nd order roll-off. An important phase noise point to note is below the loop BW, the transfer function has a gain of N.

This gain is a voltage gain and causes a phase noise increase of the reference phase noise by 20logN below the PLL loop BW. Noise transfer functions from every source can be derived in a similar approach and are summarized in the following figures. The reference noise transfer function is repeated for completeness. Noise from the divider has the same forward gain as noise from the reference, therefore the same transfer function, and is not explicitly shown. Once the gain is determined, R 1 and R F of Figure 4 can be determined.

Next C F is set so the pole in the feedback is below the loop bandwidth. Further stability considerations are provided in []. Measured data will be compared to the simulation results. Many PLL simulators exist. ADS provides an example project to use as a starting point [6]. Phase Noise is modelled for the Oscillators and the Frequency Divider. Voltage noise is modelled for the loop filter. Noise units are an important parameter to keep straight at various points in the loop.

The detector and oscillator constants K D and K o provide the conversion between noise in the voltage domain to noise in the frequency domain. The conversion to phase noise is calculated directly from the phase noise definition[ 7 ]. The Spectral Density is the power within a bandwidth divided by the bandwidth and is given by.

The first step is determining the optimum loop BW for the application. Typically the loop bandwidth is set near the frequency where the reference noise crosses the VCO noise.

This needs to be done at a common frequency to account for the 20logN increase in reference phase noise, see case 1 of Figure 7. For this example, the phase noise of the free running VCO and the reference oscillator multiplied to the output frequency are both shown in Figure For this design the loop bandwidth was chosen to be slightly higher than the optimum phase noise BW for vibration considerations and set to about 75Hz.

The simulation of the noise transfer functions from both the reference oscillator and the VCO are shown in Figure Two things to note both consistent with the earlier derivations are:. Next noise contributions of all the components in the loop are considered. Figure 15 shows the noise contributions from all the loop components including the reference oscillator, the VCO, the phase detector, the frequency divider, and the components of the loop filter.

By tracking noise contributors this way, components can be chosen for lowest noise where necessary and ignored when well below the levels of the dominant contributors. These methods were used in a recent synthesizer design. Figure 16 is a comparison of the simulated vs measured results of the phase locked loop output.

The results show very good correlation demonstrating that by accurately tracking the noise contributions of all the parts, predicted results can be achieved. He began his career at Westinghouse Corporation as an electrical field engineer on large integrated electrical systems. In addition to executing detail circuit designs, Mr. Delos has also led multi-disciplined design teams on highly integrated RF and mixed signal subsystem designs. His current interests are focused in RF and Analog designs with frequencies ranging from audio to microwave applications.

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Phase-locked loop

Phase Locked Loops are a fundamental building block in Frequency Synthesizer Design and routinely used in many applications. Much literature exists on design and simulation methods. A critical aspect of phase locked loop design for low noise applications is a clear and intuitive understanding of the noise contributions of components in various parts of the loop. This area seems to be less understood and not explicitly stated in much of the literature. Derivation of noise transfer functions and some key points for phase locked loop noise analysis is provided along with a simulation and measured example.

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The phase-locked loops are widespread in a modern radio electronics and circuit technology (Viterbi, main for the PLL theory notion of phase detector is formed exactly on the second level of Theory and Applications, World Scientific.


Design of monolithic phase-locked loops and clock recovery circuitsDa tutorial

A phase-locked loop or phase lock loop PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched.

Design and implementation of a phase locked loop for high-speed serial links

Brennan, Please note that material which is provided for reference only and is not an essential part of thecourse is distinguished by a vertical line in the left-hand margin. Some useful booksBest, R.

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frequency (RF) design and applications. 4. hashimototorii.org Phase Locked Loops. Figure 5. (Top) Experimental arrangement, (Bottom) CE


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But the technology was not developed as it now, the cost factor for developing this technology was very high. Since the advancement in the field of integrated circuits, PLL has become one of the main building blocks in the electronics technology. The block diagram of a basic PLL is shown in the figure below. The input signal Vi with an input frequency fi is passed through a phase detector.

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Skip to search form Skip to main content You are currently offline. Some features of the site may not work correctly. Razavi Published Computer Science. This paper describes the principles of phase-locked system design with emphasis on monolithic implementations. Finally, we present applications in communications, digital systems, and RF transceivers.

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